1. Field of the Invention
The present invention relates to a semiconductor packaging structure and in particular to a dual chips stacked semiconductor packaging structure.
2. Description of the Related Art
In recent years, packaging has become a performance-limiting factor for microelectronic devices, with size, weight, cost, pin count, and power consumption assuming importance in packaging design. Packaging design must generally trade off between material, structure, and electronic property considerations to obtain a cost-effective and reliable design.
Conventional stacked semiconductor packaging structure, as shown in FIG. 1, one side of a chip paddle 2 of a lead frame is usually attached to the non-active surface of the first chip 1, with the opposite side attached to the of the second chip 3 by using the epoxy or other adhesive. Wires 5 connect with the leads 4 and the bonding pads 6 deposited on the first chip 1 and the second chip 2. The resulting structure is then encapsulated by a molding compound 7, thus completing the package. It is difficult to integrate the first chip 1 and the second chip into the packaging structure since the active surfaces of the fist chip and the second chip are opposite each other. Moreover, the total thickness of the stacked packaging structure is thick.
Another conventional stacked semiconductor packaging structure is shown in FIG. 2. A spacer 30 is disposed between the first chip 100 and the second chip 20. The active surfaces of the first chip 10 and the second chip 20 face the same direction. However, the total thickness of the stacked semiconductor packaging structure as mentioned above is still overly thick. Furthermore, the stacked semiconductor packaging structure is asymmetrical, affecting reliability.